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The shift from monolithic to multi-die design is inevitable — but that's not to say it's straightforward. Traditional monolithic design has clear limitations. Diminishing yield and high cost-per-die become issues when a design nears reticle limits. At this point, multi-die integration can break the system into a series of smaller dies and to overcome scale and cost issues of scale.
Hyperscalers and other high-performance computing companies have noted that chiplets enable collaborative design within a multi-die context that delivers cost advantages and "mix-and-match integration” across heterogeneous IP blocks. Unfortunately, the chiplet ecosystem has yet to be completely standardized. Chiplet-based design incurs challenges around packaging, power delivery, verification, timing, floor planning, security, testability, and thermal management.
Together with Alchip Technologies, a high-performance computing and AI ASIC company, Synopsys addresses these issues to deliver the ROI and physical benefits of a multi-die design.
Chiplet Flexibility for Multi-Die Chip Design
This Synopsys-Alchip collaboration combines decades of IP and EDA development and expertise. Synopsys provides silicon-proven and complete IP such as 112G and 224G Ethernet, PCIe 6.0, PCIe 7.0, and UCIe, as well as industry-leading design and verification EDA tools. Alchip contributes its high-performance computing (HPC)-optimized physical design methodology, large-scale high-speed interface IP integration, and 2.5D advanced package design capabilities.
The growing demand for IO and memory chiplets—small integrated circuits (IC) that combine with other chiplets to make up a bigger system-on-chip (SoC)—drives the collaboration. The process calls for carving out the functionality contained within a monolithic die and transferring it to a smaller companion unit.
The inevitable march to advanced nodes makes monolithic SoCs progressively less efficient and expensive. A standard implementation that incorporates all aspects of functionality into a single die becomes progressively harder to manage at advanced nodes. Consequently, process optimization is one reason to adopt multi-die integration; where different parts of the system’s functionality may be improved on different technology nodes. A chiplet’s ability to add proven functions also enhances productivity and predictability, and reduces time to market.
What are Soft Chiplets: An Individualized Solution
The benefits of using multiple chiplets include improved performance, better ROI, enhanced reusability, and faster time-to-market. Implementing a multi-die design also enables flexible process node selection, improved performance, and reduced high-speed interface risk.
Drawbacks include package complexity, higher non-recurring engineering cost, more complex power, and latency considerations. The Synopsys-Alchip collaboration offers greater design flexibility and architecture optimization by providing a customizable soft chiplet, based on Synopsys IP, that users can "harden" to their application’s requirements.
This concept applies to a wide range of applications, but is particularly useful for high-performance computing, where artificial intelligence is ballooning both compute power requirements and server size. Decoupling functionality from the die allows for bigger, more complex SoCs within the package. However, it is important to recognize that one size doesn’t fit all — hence the emphasis on the flexibility of the chiplet.
The typical soft chiplet designer is not seeking a cut-and-dried solution, but rather optimization that will align with specific needs and an expansive scope for customization and modification.
Under normal circumstances, partitioning functionality across different dies is a highly complicated task. The Synopsys-Alchip solution minimizes complexity, while maximizing control with a mature, yet adaptable product, built to enable a faster development cycle. This process means the chiplet can be hardened for a specified process node and package. Configurations, die-size, and aspect ratio are also moveable. Besides shortening time-to-market, splitting monolithic SoCs frees users to concentrate on their core application-specific integrated circuit (ASIC) development. Its strength comes from combining proven technology and the abilities of two design flow specialists experienced in multi-die development.
As the move to multi-die design gathers momentum, technological limitations will depend less on a chip's capacity. The only thing holding developers back is the ease and speed with which they can create and integrate a chiplet system that makes a user-friendly, customizable solution a valuable asset that an off-the-shelf solution simply can’t beat.
Drive Multi-Die Innovation
Synopsys is empowering technology visionaries with a comprehensive and scalable multi-die solution for fast heterogeneous integration.
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3 min read
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May 09, 2024