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Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs.

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High-Speed SerDes IP Solutions

Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.

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<p><a href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_112g_ethernet_phy">112G Ethernet PH<span style="font-family: inherit;">Y IP</span></a><span style="font-family: inherit;"> enables true long reach channels for up to 800G high-performance computing SoCs</span></p><p><span style="font-family: inherit;"><a href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_56g_ethernet_phy">56G Ethernet PHY IP</a> addresses reach and performance of up to 400G Ethernet applications</span></p><p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/die-to-die.html">Die-to-Die PHY IP</a> enables up to 112G XSR connectivity</span></p><p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/multiprotocol-phys.html">Multi-Protocol PHYs</a> supports Ethernet, PCI Express, CCIX, CXL and more protocols</span></p><p><a href="/content/synopsys/en-us/designware-ip/interface-ip/pci-express.html">PCI Express PHY IP</a> enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes</p>

Comprehensive Portfolio

224G Ethernet PHY IP and 112G Ethernet PHY IP enable true long reach channels as part of the industry's first Complete 1.6T Ethernet IP Solution

56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications

Die-to-Die PHY IP for UCIe and 112G XSR

Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols

PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 128GT/s SoCs on advanced FinFET processes

Webinars & Whitepapers +

<p>Webinar: <a href="https://www.synopsys.com/designware-ip/resources/webinars/overcoming-pcie6-integration-and-validation-challenges.html?cmp=disp_ip_misc_07_14_22_1549306_wbr_ww_pcie_hhs20">Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges</a></p><p>Webinar: <a href="https://attendee.gotowebinar.com/register/1388436214572543504?source=Synopsys">PCIe 6.0 From IP to Interconnect in High-Performance Computing</a></p><p>Webinar: <a href="/content/synopsys/en-us/designware-ip/resources/webinars/minimize-latency-with-400g-800g-ethernet-ip.html">Keeping Latency to a Minimum with 400G/800G Ethernet IP</a></p><p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1474205&tp_key=82f85b7d37&sti=web">Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution</a></p><p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1466672&amp;tp_key=bc58fabe78&amp;sti=search">PCI Express 6.0 Design Considerations & IP Implementation</a></p><p>Whitepaper: <a href="https://www.synopsys.com/dw/doc.php/wp/Evolution_of_Data_Center_Networking_Technology-IP_and_Beyond_wp.pdf">Evolution of Data Center Networking Technology — IP and Beyond</a></p>

Educational Content Covering a Wide Range of Topics to Keep You Up-to-Date

Webinar: How 100G 200G Electro-Optical Interfaces Enable Low Power, Low Latency Datacenters,

Webinar: Key MAC Considerations for the Road to 1.6T Ethernet Success

Whitepaper: ESD Co-Design for High-Speed SerDes in FinFET Technologies

Webinar: The Path to 1.6TbE with 224G Ethernet PHY IP

Videos +

Now Playing: Very Short Reach SerDes In The Data Center

800G Ethernet Subsystem Link-Level Interop Success with Ecosystem at ECOC 2023

DSP Techniques For High-Speed SerDes

800G Ethernet Subsystem Linkup, FEC Stats and Performance Demo

Synopsys 224G Ethernet PHY IP at TSMC Symposium

Synopsys and OpenLight Electro-Optical Link Demo

Synopsys 224G, 112G Ethernet PHY IP and PCIe 6.0 IP at DesignCon 2023

Synopsys 224G and 112G Ethernet PHY IP Demonstrations at OIF & OFC 2023

Latest News +

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Stay Current with the Latest News on High-Speed SerDes IP

Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry’s First PCIe 7.0 IP Solution

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability,

100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers

The Controller Designers Need for 1.6 Terabits per Second Ethernet Interfaces

Latency Considerations For 1.6T Ethernet Designs

Synopsys Demonstrates Industry’s First Interoperability of PCI Express 6.x IP with Intel’s PCIe 6.x Test Chip

Podcasts +

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Stay Current with the Latest Podcasts on High-Speed SerDes IP

How Are the Standards for the Terabit Era Defined?

800Gs Finally Breaking out and Benefits of Solution

The Impact of UCIe on Multi-Die Systems

Application Challenges to get to 1.6T using 224G Ethernet

How an ASIC Model for IP Can Accelerate Semiconductor Innovation

The Role of Synopsys High-Speed SerDes for Future Ethernet Applications

An All Inclusive Journey to HPC/Data Center Silicon Success

Featured Resources

Blog

How PCIe 7.0 is Boosting Bandwidth for AI Chips

Article

How Direct-Drive Electro-Optical Interfaces are Changing the Game for 800G & Beyond

Article

Navigating PCIe 6.x Power and Latency Challenges in HPC SoCs

Blog

How OpenLight and Synopsys Are Reimagining Data Centers Through Silicon Photonics

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