Synopsys Duet Packages
The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrated portfolio of standard cell libraries, memory compilers and memory test and repair capability. The optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs) provide all the elements needed to implement a complete system-on-chip (SoC). Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the highest quality of results for their SoC in their specific application.
An additional High Performance Core (HPC) Design Kit provides a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of the three.
Synopsys Embedded Memories and Logic Libraries are available for multiple foundries and process technologies, including GLOBALFOUNDRIES, Huali, SMIC, TSMC, and UMC.
Synopsys Foundation IP for GF 22FDX Datasheet Synopsys Foundation IP for GF 40LP Datasheet Synopsys Foundation IP for GF 55LPe Datasheet Synopsys Foundation IP for HUALI 40LP Datasheet Synopsys Foundation IP for HUALI 55LP Datasheet Synopsys Foundation IP for SMIC 40LL Datasheet Synopsys Foundation IP for SMIC 65LL Datasheet Synopsys Foundation IP for TSMC 16FF+ Datasheet Synopsys Foundation IP for TSMC 16FFC Datasheet Synopsys Foundation IP for TSMC 22ULL Datasheet Synopsys Foundation IP for TSMC 28HP Datasheet Synopsys Foundation IP for TSMC 28HPC Datasheet Synopsys Foundation IP for TSMC 28HPC+ Datasheet Synopsys Foundation IP for TSMC 28HPM Datasheet Synopsys Foundation IP for TSMC 40LP Datasheet Synopsys Foundation IP for TSMC 65LP Datasheet Synopsys Foundation IP for TSMC N4P Datasheet Synopsys Foundation IP for TSMC N5 Datasheet Synopsys Foundation IP for TSMC N5A Datasheet Synopsys Foundation IP for TSMC N6 Datasheet Synopsys Foundation IP for TSMC N7 Datasheet Synopsys Foundation IP for UMC 28HLP Datasheet Synopsys Foundation IP for UMC 28HPC Datasheet Synopsys Foundation IP for UMC 40LP Datasheet Synopsys Foundation IP for UMC 40ULP Datasheet
- All the elements needed to implement a complete SoC, including high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs)
- High-density embedded SRAMs optimized to generate the absolute minimum area and power enable designers to achieve aggressive area and power budgets
- Multiple levels of memory power management features. Light Sleep, Deep Sleep and Shut Down modes enable array biasing with partial periphery shut down, full periphery shut down with data retention and a complete shut down without data retention
- Yield-optimized standard cells with multiple threshold voltage and channel length variants