With advancements in technology and the push towards smaller nodes from 7nm down to 3nm, designs are expected to work under different modes, with possibly different clock frequencies along with a range of global variations. Thus, designs have to achieve signoff closure for timing and power across an enormous number of process, voltage, and temperature (PVT) corners.
Characterizing this huge number of PVT corners, library teams across the industry face further challenges like high simulation turnaround time, database disk space limits, license server overloads, and hardware costs.