What is Silicon Lifecycle Management?

Synergies between the Synopsys Test and Silicon Lifecycle Management (SLM) product families ensure the highest quality, lowest cost test and optimal silicon health for your device. Integrated tools, IP and methodologies provide actionable insights by testing, monitoring and analyzing at every phase of the device lifecycle. The unified solution delivers enhanced performance, eases implementation and minimizes impact on design PPA.

SLM adapts test and screening criteria through ongoing analysis of silicon and manufacturing test result data. Optimized test criteria will reduce test time and ensure only good devices are released to production.

Sources of this data include manufacturing test results, process/voltage/temperature (PVT) monitor data and structural monitor data. Through a process of data mining, monitoring/analysis and reporting, adaptive test alerts and enhanced control measures can be implemented. The ability to detect outliers, or chips that exhibit performance outside of normal limits, is also enhanced.

The result is reduced test time and improved quality of the delivered chip.

In any complex chip, there are interactions between hierarchical interconnects, heterogeneous processors, various operating systems and bare metal software. All these interactions must be harmonized in order get the chip and the system that uses it to market. Adding to this challenge is the fact that most systems are designed without really knowing what the workload will look like when the final system is deployed.

SLM can address these challenges through deep insight into the functionality of the compute, communication and storage resources on a chip. The combination of functional and structural monitors embedded in the chip, together with analysis software enable much faster and deeper understanding of the behavior of the chip’s operation and how it interacts with the overall system. In addition, during the life of the system, workloads change, software and firmware requirements change and transistors age. SLM also provides insights to allow the chip and system to adapt to these changes. The result is shorter development time, improved validation efficiency and better long-term performance.

The performance of a silicon chip does not remain constant over its operating life. Aging effects in the silicon structures change the performance characteristics of the device over time. The system operating environment can also contribute to changes in chip performance. These effects include environmental temperature effects, process variation, voltage supply fluctuation and the impact of changes in workload and electrical operating parameters. Security breaches can also impact chip performance.

Semiconductor devices are performing more mission critical and safety-related functions in systems today. This makes the robustness and reliability of these devices more important. Many of these systems have a long operating life, and time also contributes to the gradual change in performance of semiconductor devices.

Silicon lifecycle management provides a data collection, analysis and control environment to monitor all of these effects and implement corrective actions in the field at a unit device level. The result is far more stable and secure performance of the silicon device and overall system over time.

The Synopsys Silicon Lifecycle Management Family includes multiple integrated products and capabilities. The key components of this end-to-end solution are highlighted below:
 

• Synopsys SLM environmental, structural and functional monitoring IP combined with existing (DFT) and built-in self-test (BIST) resources provides the rich set of silicon data which forms the foundation of the Silicon Lifecycle process
  
  
• Synopsys TestMAX™ and the Synopsys Digital Design Family RTL-to-GDSII solution provide automated integration of the Synopsys SLM Platform monitors and analytics tools into the RTL or gate-level design
  
  
• The Synopsys SLM Family links Synopsys TestMAX to the golden signoff solution Fusion Digital Design Family for guidance on optimal placement of the Synopsys SLM embedded monitors
  
  
• Synopsys Digital Design Family closes the loop on design implementation by leveraging silicon data-based timing model calibration to minimize required margins as well as advanced analytics to further optimize design power, performance and area (PPA), reliability and silicon predictability
  
  
• Synopsys High-Speed Access & Test (HSAT) IP provides adaptive high bandwidth testing over functional interface as well as high speed access to DFT & Silicon monitoring network through entire Silicon Lifecycle
  
  
• Synopsys TestMAX™ ALE enables an extremely high, test bandwidth for die testing to in-system test and on to all stages of the product lifecycle
  
  
• Synopsys Optimizer provides performance optimization software to improve compute system performance, automatically and in real-time