Cell library characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.
Knowing the logical function of a cell is not sufficient to build functional electrical circuits. More aspects need to be considered; for example, the speed of a single cell will influence the speed of the full circuit, just as the power used by a single cell can influence the total power. Further, the speed as well as the power might be influenced by the output load. Standard-cell characterization aims at collecting this sort of information.
Library characterization is a process of simulating a standard cell using analog simulators to extract input load, speed, and power data in a way that the downstream tools can process it all. This can be done via a specific analog simulator whose output is used to generate the characterization data, or by using a library characterization tool.
For digital library characterization, some of the views are usually provided by the design while others must be derived. For instance, the logic function of a NAND gate could be defined as "!(A & B)." In principle, all other views can be derived from this equation using some additional assumptions and constraints, depending on the technology and design goals. The netlist of combinatorial cells can be generated algorithmically. Starting from the netlist, a layout will be drawn which can be used to extract parasitic capacitances and resistances within the cell. The resulting netlist of transistors and parasitics can be further used to get an abstract description of the cell’s timing, power, and noise behavior.
One way to derive timing and power numbers is through simulation of the transistor netlist. However, one simulation is not enough because the cell’s behavior strongly depends on other factors, such as process, voltage, and temperature (PVT), input wave form, and output load. A common approach is to look at the best and worst PVT conditions. Effectively, this allows you to predict lower and upper bounds of the cell behavior, which are important to ensure the overall functionality of the design. Further, cells must be characterized over a reasonably large range of input edge rates and output load. For example, a cell could be characterized on a two-dimensional grid with variable input edge rate and output load (non-linear delay model). If the grid points are chosen correctly, then the behavior between grid points can be approximated by linear interpolation.
Cell library characterization typically takes cell design extracted as SPICE circuit and SPICE technology models. The characterization tool analyzes this information to:
Digital chip design is not possible without cell library models. These models are produced by cell library characterization. Every digital chip implementation RTL-to-GDSII flow requires cell library models for analysis (logic simulation, verification, timing, power, noise, etc.), implementation (synthesis, test insertion, placement, clock tree synthesis, routing) and fixing (engineering change order, rule fixing, etc.).
Standard cells must be characterized so that they can be processed by the various tools in the CAD flow. The synthesis tools, for example, need to know the logic function of the cell, the load that the cell input will present to a signal connecting to it, the speed of the cell under different input slope and output loading conditions, the power that the cell will consume, and the area of the cell in order to do a good job of synthesizing a behavioral description to a collection of standard cells.
Library characterization plays a key role in the drive towards achieving higher power, performance, and area (PPA) metrics in less design time. A large portion of chip area consists of digital logic, memories, I/O, and custom IP designed and implemented by static timing analysis-based digital methodologies that use Liberty models that are derived from library characterization. Therefore, the ability to characterize libraries efficiently and accurately across all intended PVT conditions is a critical requirement for full-chip or block-level design flows. Cell library characterization produces the following outputs:
Verilog
Verilog models are most often used in the design and verification of digital circuits at the register-transfer level of abstraction. These Verilog models are further synthesized into the gate-level netlist.
IBIS
IBIS is the standard for describing the analog behavior of buffers of the digital IC’s pins (input, output, and I/O buffers) in plain ASCII-formatted text (behavioral model) without revealing the underlying circuit’s structure or process information. Advantages of IBIS include:
Liberty
The Liberty format is an ASCII file that describes a cell’s characterized data in a standard way. This file is used both by the synthesis tools and by the place-and-route tools. It simply describes the overall structure of the file. Liberty file format is very complex with huge numbers of special statements that can describe all sorts of parameters that would be relevant to the different CAD tools that use this format to get information about the standard cells in the library.
The Liberty model consists of delay, transition time, tristate, input capacitance, hidden power, dynamic power, leakage power, setup time, hold time, recovery time, removal, minimum pulse width, output current waveform, input receiver capacitance, power supply waveforms, ground waveforms, leakage current, gate leakage current, CCB output voltage waveform, CCB input miller capacitance, CCB noise propagation model, statistical models, and moment models.
Synopsys offer PrimeLib and NanoTime as solutions for library characterization.
The PrimeLib solution includes a comprehensive array of library characterization and quality assurance (QA) capabilities that are tuned to produce PrimeTime® signoff-quality libraries with maximum throughput on available compute resources. The innovative technologies encompassing PrimeLib utilize embedded gold reference SPICE engines to provide a characterization speed-up of advanced Liberty models used by PrimeTime static timing analysis (STA) to accurately account for effects seen in ultra-low-voltage FinFET processes that impact timing. This includes PrimeTime parametric on-chip variation (POCV), advanced waveform propagation (AWP), and electromigration (EM) analysis. PrimeLib is cloud-ready, and with its optimized scaling technology accelerates throughput on cloud or on an on-premise cluster.
NanoTime, the key foundry-certified, golden signoff solution for transistor-level design, performs transistor-level static timing, signal integrity, and process variation analysis for complex custom designs such as CPU datapaths, register files, embedded memories, and analog mixed-signal IP blocks. For advanced-node designs, such as those using FinFETs, the cost of silicon failure is very significant, making signoff analysis critical to ensure that the design is free from fatal timing and noise problems. Complementing dynamic simulation, NanoTime can exhaustively check for all internal timing and noise interactions. It creates block-level timing models that can be used with PrimeTime for full-chip signoff. NanoTime integrates seamlessly with the Synopsys Custom Compiler® custom design environment and with StarRC™ Custom Ultra+ to read layout parasitics. It can also leverage Synopsys simulators HSPICE and FineSim to deliver the highest accuracy.
