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Vietnam Seminar 2024
Silicon to System: Our Technology, Your Innovation
Event Details
Ballroom 1-2, Level 3
Sheraton Saigon Hotel
88 Dong Khoi Street, District 1
Ho Chi Minh City, Vietnam
Date: Friday, July 12, 2024
Time: 8:30am - 4:45pm
Today, we find ourselves at the nexus of the fourth industrial revolution — an era dominated by Smart Everything. The internet, artificial intelligence, and the use of software are helping to create things that couldn’t even be imagined just a decade or two ago. The opportunities seem limitless, and the potential for more world-changing technologies are bound only by our dreams. Synopsys is on the move from “Silicon to Systems”!
Join us for an exciting day at Sheraton Saigon Hotel and be empowered to fashion the “Our Technology, Your Innovation” with innovations and new technologies. Our executive speakers will share their vision of innovations in the semiconductor industry, and you will also be hearing from our guest speakers on their latest advancements and innovations in a rapid growth industry. It is the first time; we will have a dedicated session to present Synopsys latest emulation technology that based on ZeBu Server 5 hardware system.
We will be offering two separate tracks in the afternoon focusing on various aspects of implementation, verification, and other technologies that are mission critical to catalyzing a new era of pervasive intelligence.
We look forward to seeing you!
Vietnam Seminar
Friday, July 12, 2024
8:30 - 9:00 AM
Ballroom 1-2, Level 3
9:00 - 9:30 AM
Ballroom 1-2, Level 3
A Strategic View of IC Design and Semiconductor Industry in Vietnam Toward 2030 and Beyond
Dr. Nguyen Thien Nghia, Director of ICT Industry Dept. of MIC
9:30 - 10:10 AM
Ballroom 1-2, Level 3
Evolution of IP Multi-die System Trans
John Koeter, SVP, Solutions Group, Synopsys
10:10 - 10:45 AM
Ballroom foyer
Coffee/Tea Break
10:45 - 11:30 AM
Ballroom 1-2, Level 3
How Synopsys.ai is Driving the Next Wave of Innovation in EDA
Abhijeet Chakraborty, Vice President of Engineering, EDA Group, Synopsys
11:30 - 12:00 PM
Ballroom 1-2, Level 3
Accelerating SoC Design with Hardware Assisted Verification
Thomas Li, VP, System Design Group, Synopsys
12:00 - 1:30 PM
Saigon Café, Level 1
Lunch (Networking)
1:30 - 2:00 PM
Ballroom 1-2, Level 3
Enabling the Next Generation of VLSI Designs with Silicon Lifecycle Management and AI Driven Test
Vo Huu Chau Uyen, Sr Manager, Synopsys
1:30 - 2:00 PM
Ballroom 3, Level 3
Enhance Clock Domain Crossing (CDC) Verification Efficiency by Adapting VC Spyglass CDC to RTL and Huge-scale Designs
Hoang Hai Vu, Senior Staff Engineer, Renesas Design Vietnam
2:00 - 2:30 PM
Ballroom 1-2, Level 3
Improving Productivity and TAT using ICV
Vikas Gupta, Senior Director, Synopsys
2:00 - 2:30 PM
Ballroom 3, Level 3
Accelerate SVA Verification with IDX for SoC Complex Design
Ta Nguyen Thanh Hung, Manager, Renesas Design Vietnam
2:30 - 3:00 PM
Ballroom 1-2, Level 3
Improve CTS QoR by H-tree-only Regular MSCTS for Complex Floorplans and Notches Design
Pham Kim Luan, Senior Engineer, Quest Global Vietnam
2:30 - 3:00 PM
Ballroom 3, Level 3
Next-Generation Verdi: Overview of New Debug and Verification Management
Allen Hsieh - Applications Engineering Manager, Synopsys
3:00 - 3:45 PM
Ballroom 1-2, Level 3
Update on ASO.ai Circuit Optimization and PrimeSim Design Robustness
Jiang Xi, Senior Staff AE, Synopsys
3:00 - 3:45 PM
Ballroom 3, Level 3
HW–SW System Validation in FPGA and Emulator Mode
Patrick Heng, Senior Director, Synopsys
3:45 - 4:15 PM
Ballroom foyer
Coffee/Tea Break
4:15 - 4:45 PM
Ballroom 1-2, Level 3
Lucky Draw
