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Synopsys IP Videos
800G Ethernet Subsystem Link-Level Interop Success with Ecosystem at ECOC 2023
Watch our 800G demos at ECOC'23 using 8 lanes of LR 112G Ethernet PHY IP & 800G MAC/PCS interop with exercisers, analyzers & 3rd Party 800G EVBs over DAC Channels showing linkup, packet receive/transfer, FEC histogram & other performance metrics.
Synopsys’ Silicon-Proven USB 3.2 Device IP Operating at 20 Gbps
This video features Synopsys silicon-proven USB 3.2 Device IP, implemented in FPGA, operate at 20Gbps with three different hosts.
World’s First PCIe 6.0 Interop with Intel’s PCIe 6.0 Test Chip at Intel Innovation 2023
See the Synopsys IP for PCIe 6.0 & Intel's PCIe 6.0-enabled test chip successful interop, a milestone for PCIe tech. The demo showcases link robustness @ 64GT/s and multiple speed changes using Synopsys & Intel HW and a Teledyne LeCroy Summit M616.
What’s New with Non-Volatile Memory (NVM) IP?
Understand the market changes driving NVM IP development, how the global wafer shortage is affecting NVM IP selection, and the latest development plans for Synopsys NVM IP.
AI SoC Chats: Understanding Compute Needs for AI SoCs
Will your next system require high performance AI? Learn what the latest systems are using for computation, including AI math, floating point and dot product hardware, and processor IP.
Achieving Higher Safety and Security in Autonomous Vehicles (Episode 1)
Learn how automotive chip design is evolving as the large numbers of sensors being integrated in these systems increases system complexity and drives up processing requirements.
Fast & Accurate 3D Object Detection for LiDAR with Synopsy ARC EV Processor IP
This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on ARC EV7x processor with DNN engine. It shows 3D boxes rendered onto objects detected in the video frames, enabling the development of driver assistance systems.
Meeting Cloud Data Bandwidth Requirements with HPC IP
As people continue to work remotely, demands on cloud data centers have never been higher. Chip designers for high-performance computing (HPC) SoCs are looking to new and innovative IP to meet their bandwidth, capacity, and security needs.
Silicon-Proven Automotive-Grade Synopsys IP
Get the latest on Synopsys' automotive IP portfolio supporting ISO 26262 functional safety, reliability, and quality management standards, with an available architecture for SoC development and safety management.
Broad Portfolio of IP for Mobile SoCs
Get the latest update on Synopsys IP for mobile SoCs, including MIPI C-PHY/D-PHY, USB 3.1, and UFS, which provide the necessary throughput, bandwidth, and efficiency for today’s advanced mobile SoCs.
Synopsys and SK hynix Discuss HBM2E at 3.6Gbps
In this video interview hear from Keith Kim, Team Leader of DRAM Technical Marketing at SK hynix, discussing the wide adoption of HBM2E at 3.6Gbps and successful collaboration with Synopsys to validate the HBM2E IP at the maximum speed.
Synopsys MIPI C-PHY/D-PHY IP Performance at 24 Gbps
This video features the Synopsys MIPI C-PHY/D-PHY IP interoperating with an image sensor in C-PHY mode up to 3.5 Gsps per trio and D-PHY mode up to 4.5 Gbps per lane, available in FinFET processes for camera and display applications.
Product Update: Advances in Synopsys Die-to-Die PHY IP
Hear the latest about Synopsys' Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP addresses the power, bandwidth, and latency requirements of SoCs targeting hyperscale data center, AI, and networking applications.
LE Audio Over Bluetooth with Synopsys IP
The video shows the new LE Audio using Synopsys’ Bluetooth 5.2 PHY IP and Link Layer IP with isochronous channels, and ARC Data Fusion IP Subsystem with ARC EM9D Processor, running the LC3 codec supporting LE Audio.
Hardware Security Verification Using Tortuga Logic Radix-S Software at ARC Summit 2019
Understand hardware security verification using the Tortuga Radix Software, which allows you to identify system-level security vulnerabilities that can exist at both the hardware and software levels.
Automotive Trends Driving New SoC Architectures
The use of IP is prevalent in today’s new AI-enabled automotive SoCs for safety-critical ADAS applications. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet your evolving SoC design requirements.
IP Driving Automotive SoCs
If you are designing SoCs for ADAS, where safety and reliability are non-negotiable and a split second matters, then you want to know about Synopsys IP for Automotive.
Maximizing SoC Throughput with Synopsys CCIX IP
This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX PHY and controller IP.
Test & Repair Requirements for Autonomous Vehicles
Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.
IP for Machine Learning Applications
The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements.
55-nm IoT Platform
This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.
What is ASIP Designer?
See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements.
Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio
John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.
SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching
See how Synopsys SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth.
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