VC Verification IP for USB Power Delivery

Highlights

• Native SystemVerilog/UVM
• Source code test suite available (optional)
• Runs natively on major simulators
• Built-in protocol checks
• Verification plan and coverage
• Verdi Protocol Analyzer
• Extensive error injection

Key Features

• USB PD 3.0 and PD 2.0
• Policy layer disable mode to exercise PD messages directly onto Protocol and PHY layers
• Option of emulating Cable Plug within a single agent
• Extended messages
• Provider and Consumer
• All Resets: Hard, Soft and Cable Reset
• Structured VDM
• Collision generation and Avoidance
• Error scenarios
• DFP, UFP, Cable Plugs
• Power negotiation
• Power, Data, and VCONN role swap
• BIST