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TSMC & Synopsys
Collaborate to Innovate
Power and Performance-Optimized Methodologies for Next-Generation Designs
TSMC, a leading semiconductor foundry, and Synopsys have successfully collaborated for decades to deliver mutual customers optimized solutions for TSMC’s wide range of process technologies from 180nm to 2nm. The collaboration provides designers with the industry's most comprehensive IP, EDA tools and design flows, including multi-die systems, on TSMC's advanced process technologies with support for TSMC 3DFabric™ technologies and the TSMC 3Dblox™ standard.
Key Benefits
Certified Digital & Custom Design Platforms
Design complex SoCs with greater confidence
Long-Standing Collaboration
20+ years of semiconductor evolution
Minimize IP Integration Risk
Synopsys DesignWare IP optimized for TSMC's most advanced processAreas of Collaboration
Seamless Design Flows and Certified Design Tools
With the evolution of process technologies, TSMC and Synopsys have anticipated the design challenges for each new process technology generation and have identified new design implementation issues. To help designers work within increasing technical constraints and stricter product requirements, we are continuously working towards tool certification and technology for the latest nodes. We collaborate in advanced FinFET technology, enhanced timing and statistical design, multi-die systems using 3DFabric™, analog mixed signal, and custom design.
Silicon-Proven IP for TSMC Processes
For more than 20 years, Synopsys and TSMC have collaborated to deliver a high-quality Interface IP and Foundation IP portfolio for TSMC’s process technologies from 180-nm to 3-nm, targeting a range of applications including HPC, AI, automotive, and mobile. With the high-quality IP portfolio, designers can align their aggressive project schedule and design requirements, while optimizing PPA, bandwidth and latency. To meet the stringent reliability and operation requirements of ADAS SoCs, leading automotive OEMs, Tier 1s, and semiconductor providers have adopted Synopsys’ automotive-grade IP for TSMC processes. With the broad adoption of DesignWare IP and customer silicon successes, Synopsys enables designers to integrate the IP with confidence and significantly lower SoC integration risk.
Cloud Solutions and OIP Virtual Design Environment
Synopsys design solutions are certified for TSMC’s Open Innovation Platform Virtual Design Environment (VDE) to run on Amazon Cloud (AWS), Microsoft Azure, and Google Cloud Platform (GCP). The combination of these industry-leading cloud platforms and Synopsys design tools for the cloud enable system-on-chip (SoC) designs with easy hardware scaling to boost design implementation and signoff productivity.
Design Services Partnership
Synopsys Professional Services has created an integrated flow with best-in-class technology providers that enable us to offer a comprehensive set of chip development services for TSMC processes.
Synopsys
The advancements in Synopsys' production-ready EDA flows and photonics integration with our 3DIC Compiler, which supports the 3Dblox standard, combined with a broad IP portfolio enable Synopsys and TSMC to help designers achieve the next level of innovation for their chip designs on TSMC's advanced processes. The deep trust we've built over decades of collaboration with TSMC has provided the industry with mission-critical EDA and IP solutions that deliver compelling quality-of-results and productivity gains with faster migration from node to node.
Sanjay Bali
Vice President of Strategy and Product Management for the EDA Group, Synopsys
TSMC
Our close collaboration with Open Innovation Platform (OIP)® ecosystem partners like Synopsys has enabled customers to address the most challenging design requirements, all at the leading edge of innovation from angstrom-scale devices to complex multi-die systems across a range of high-performance computing designs. Together, TSMC and Synopsys will help engineering teams create the next generation of differentiated designs on TSMC's most advanced process nodes with faster time to results.
Dan Kochpatcharin
Head of Design Infrastructure Management Division ,TSMC
Synopsys
New generations of automotive SoC designs will need to support massive amounts of safety-critical data processed at extreme speeds and with high reliability. Synopsys' high-quality, automotive-grade Interface and Foundation IP on TSMC's N5A process enables automotive OEMs, Tier 1s, and semiconductor companies to minimize IP integration risk and help meet the required functional safety, performance, and reliability levels for their SoCs.
John Koeter,
Senior Vice President of Marketing and Strategy for IP, Synopsys