RTL Synthesis Track
 

This 12-week track comes with everything you need to know about RTL Synthesis and gives you hands-on experience with Synopsys tools like Design Compiler NXT, Formality, and Fusion Compiler.​​​​​​​
 

RTL Synthesis I:  Foundation - This introduction covers the hardware description languages Verilog/VHDL and SystemVerilog used to model ASIC designs.

RTL Synthesis II: Comprehensive - In this course you will learn the RTL synthesis flow, specifically when using Design Compiler NXT in topographical mode. You will learn how to synthesize a block-level RTL design to generate a final gate-level netlist with acceptable post placement timing and congestion. The course will teach Synopsys recommended methodologies for different synthesis optimization techniques and constraining the design.

Design Compiler NXT: Foundation Exam - Take this exam to demonstrate the knowledge acquired from design creation and synthesis course.

Formality -  In this course you will apply a formal verification flow for design verification and debugging of failed design. You will apply an extended flow to optimize Formality for common hardware design transformations. Increase debugging capability through techniques such as pattern analysis and maximize the verification performance.

UPF Fundamentals - This course will provide an overview and benefits of different power-saving techniques that can be achieved through UPF, highlighting areas of concern when adopting these techniques that could impact your implementation and verification schedule. The course will go through the caveats of UPF power domain creation, covering the concepts of 'good power design partitioning' to achieve optimal results. Top-down and hierarchical approaches to power domain creation are covered as well as the link between the conceptual UPF power domain definition and how that tie into the physical flow. The concepts of "supply net" and "supply set" are touched upon, covering levels of abstraction that each individual construct offers, providing SoC-based or IP-based engineers with a mechanism to implement and verify the power domain architecture of choice.

UPF Fundamentals Exam - Take this exam to demonstrate the knowledge acquired from UPF fundamentals course.​​​​​​​

Design Compiler NXT: Clock Gating Low Power - This is an advanced course on Design Compiler NXT and will teach you how to properly set up the tool for doing power analysis by applying switching activity and to perform power optimizations technologies such as clock gating, self-gating, multibit register banking, low power placement and DesignWare minPower.

Design Compiler NXT: Clock Gating Low Power Exam - Take this exam to demonstrate the knowledge acquired from Design Compiler Low Power course.

Duration: 12 weeks (includes 5 weeks for prerequisites)

Cost: $2100 USD

Exam Details: Answer 25-50 questions in 60-90 minutes and achieve an 85% or higher score to pass the exam and get awarded a badge for each exam.

Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Purple Certification: RTL Synthesis Learning Path completion certificate and a digital badge. 

Design Verification Track
 

This 12-week track comes with everything you need to know about design verification and gives you hands-on experience on SystemVerilog, SystemVerilog with UVM, and Synopsys tools such as the VCS^® tool and the Verdi^® Debug Environment.​​​​​​​

Design Verification I: Foundation - This introduction covers the hardware description languages Verilog/VHDL and SystemVerilog, which are used to model ASIC designs and testbenches for verification.

Design Verification II: Comprehensive - In this course, you will learn about SystemVerilog as a hardware verification language with practical design examples.

SystemVerilog Testbench - In this course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in simulations based on the VCS tool.

SystemVerilog Testbench Exam - This exam enables you to demonstrate the knowledge required to develop SystemVerilog testbenches using UVM base classes. 

SystemVerilog Assertions - In this course, you will learn the key features and benefits of the SystemVerilog Assertion (SVA) language and its use in VCS tool-based verification.

SystemVerilog Assertions Exam - This exam enables you to demonstrate the knowledge required to write SystemVerilog Assertions and verify a device-under-test (DUT) using the Synopsys VCS® tool.

SystemVerilog for Formal Verification - In this course, you will learn the SVA language and how to write properties in your design for the VC Formal^™ tool.

SystemVerilog Verification Using UVM - In this course, you will learn how to develop a UVM based SystemVerilog testbench environment which enables efficient test case development.

SystemVerilog Verification using UVM Exam - This exam enables you to demonstrate the knowledge required to develop SystemVerilog testbenches using UVM base classes.

Duration: 12 weeks (includes 5 weeks for prerequisites)

Cost: $2100 USD

Exam Details: Answer 25-50 questions in 60-90 minutes and achieve an 85% or higher score to pass the exam and get awarded with a badge for each exam.

Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Purple Certification: Design Verification Learning Path completion certificate and a digital badge.

DFT Track
 

This 12-week track comes with everything you need to know about Design for Testability (DFT) in the ASIC design flow. It covers the need for test, fault modeling, test insertion methods, automatic test pattern generation (ATPG), concept of test coverage, and advanced test techniques.​​​​​​​
 

Design For Test I: Foundation - This introduction covers DFT, including testing of ICs, wafer sorting, defect-fault mapping, fault modeling, fault simulation, concept of DFT testability, ATPG generation, and advanced test techniques.

Design For Test II: Comprehensive - In this course, you will learn about how to use DFT with Synopsys TestMAX^™ Advisor, scan the design flow with DFT and Diagnosis, fault simulation, and test insertion using TestMAX DFT

Design For Test III- Jumpstart with Synopsys Tools

• TestMAX DFT: Jumpstart - You will learn to use TestMAX DFT to perform gate-level DFT rule checks, fix DFT DRC rule violations, insert scan using top-down and bottom-up flows, and export the results to downstream tools.
• TestMAX Manager: Jumpstart - Get an overview of the TestMAX Manager flow for generating and instantiating DFT IP, such as DFTMAX Scan Compression, On-Chip Clock Controller, etc. into a user RTL.
• TestMAX SMS: Jumpstart - Memories are complex and well structured. Testing memories involves an in-depth understanding of their function both logically and physically. Each memory has a different configuration and the test mechanism used to test the memory needs to be customized as per its architecture. Learn about how to address this requirement using Synopsys’ TestMAX Star Memory System (SMS) In this training, we will briefly discuss the SMS architecture for different memory configurations and accessing these memories from the SOC level.

TestMAX DFT – Learn in depth how to use Synopsys TestMAX™ DFT to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. Explore essential techniques to support large, multimillion gate SoC designs including the bottom-up scan insertion flow in the logical (Design Compiler®) domain.

TestMAX DFT Exam - This exam enables you to demonstrate the knowledge required to use TestMAX™ DFT for DFT rule checks and scan insertions in SoC designs.

TestMAX Advisor – Learn to use Synopsys TestMAX™ Advisor (previously known as SpyGlass® DFT) to perform RTL testability analysis that allows you to fine-tune your RTL early in the design cycle. This enables you to verify the design scan readiness and test robustness and work toward meeting fault and test coverage goals.

TestMAX Advisor Exam - This exam enables you to demonstrate the knowledge required to use TestMAX Advisor for RTL testability analysis and design scan readiness.

TestMAX ATPG - You will learn how to use TestMAX ATPG to generate test patterns for stuck-at faults given a scan gate-level design created by TestMAX DFT or other tools, and describe the test protocol and test pattern timing using STIL.

TestMAX ATPG Exam – This exam enables you to demonstrate the knowledge required to use TestMAX ATPG to generate test patterns for stuck-at faults in SoC designs.

Fusion Compiler: DFT Synthesis - In this course, you will learn about using Fusion Compiler to perform Scan Synthesis. Course starts with fundamentals of Scan testing, the supported Scan synthesis flows in Fusion Compiler, running and debugging Design Rule Checks, and then proceeds to building scan chains at the block-level.

Fusion Compiler: DFT Synthesis Exam: This exam enables you to demonstrate the knowledge required to use Fusion Compiler with DFT synthesis for DRC checks and building scan chains for the design.

Duration: 12 weeks (includes 5 weeks for prerequisites)

Cost: $2100 USD

Exam Details: Answer 25-50 questions in 60-90 minutes and achieve an 85% or higher score to pass the exam and get awarded with a badge for each exam.

Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Purple Certification: DFT Learning Path completion certificate and a digital badge.

AMS Circuit and Layout Design Track

This 12-week track comes with everything you need to know about the analog and mixed signal (AMS) circuit and layout design flow.

AMS Circuit and Layout Design: Foundation - This introduction covers analog circuit fundamentals, circuit elements (resistors, capacitors), basic circuit topologies (MOSFET structures as resistors, amplifiers, PLL and Data converters), their equivalent models, current sources, feedback theory, degeneration, equivalent model parameters and circuit design techniques and stability analysis with examples.​​​​​​​

AMS Circuit and Layout Design: Comprehensive - In this course, you will learn about VDSM analog design fundamentals and circuit behaviors of components used. Analog functions and components including op-amps, PLLs, passive devices are covered. The course also includes an introduction to PDK, design of standard cells, inverter, and op-amp reference circuits. This includes demonstrations of circuit designs using the Custom Compiler^™ tool. The course also includes an introduction to the mixed signal circuit design flow.

Custom Compiler: Foundation - Custom Compiler is a complete design platform that includes all the functionality necessary to design custom digital, analog, or mixed-signal integrated circuits (ICs). In the Custom Compiler Introduction to the Platform course, you will learn how to invoke Custom Compiler and to use basic features. 

Custom Compiler Foundation Exam - Take this exam to demonstrate the knowledge acquired on Custom Compiler platform for designing analog and mixed signal integrated circuits.

Custom Compiler: Schematic Entry - In this course, you will jump start into Custom Compiler design methodology. You will learn to use the Custom Compiler tool to perform analog schematic circuit design and verification. You will also learn about the Custom Compiler co-design flow.

Custom Compiler Schematic Entry Exam - This exam enables you to demonstrate the knowledge required to perform schematic entry of the analog designs using custom compiler.

Custom Compiler: Basic Layout Design - In this course, you will learn about basic layout editing features using the Custom Compiler Layout Editor tool and other Custom Compiler tools and assistants. 

Custom Compiler Basic Layout Design Exam - This exam enables you to demonstrate the knowledge required to edit analog circuit layouts using Custom Compiler layout editor.

PrimeSim SPICE Simulation & Analysis in the PrimeWave Design Environment – In this course, you will learn about the analog circuit simulation and debug procedure using PrimeSim^™ SPICE Simulation and Analysis in the PrimeWave^™ Design Environment.

PrimeSim SPICE Simulation & Analysis in the PrimeWave Design Environment Exam: This exam enables you to demonstrate the knowledge required to simulate and analyze analog designs using PrimeSim SPICE simulator and PrimeWave Design Environment.

Duration: 12 weeks (includes 5 weeks for prerequisites)

Cost: $2100 USD

Exam Details: Answer 25-50 questions in 60-90 minutes and achieve an 85% or higher score to pass the exam and get awarded with a badge for each exam.

Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Purple Certification: AMS Circuit and Layout Design Learning Path completion certificate and a digital badge.