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Synopsys IP for PCI Express (PCIe) 6.x
Overview
Synopsys IP for PCI Express (PCIe) 6.x complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and Integrity and Data Encryption (IDE) security module IP.
Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys IP complete solution for PCI Express (PCIe) 6.x is optimized to support the latest PCIe 6.x specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.x designs.
Navigating PCIe 6.x Power and Latency Challenges in HPC SoCs
World’s First PCIe 6.x Interop with Intel’s PCIe 6.0 Test Chip at Intel Innovation 2023
Synopsys Demonstrates Industry’s First Interoperability of PCI Express 6.x IP with Intel’s PCIe 6.x Test Chip
How PCI Express Gives AI Accelerators a Super-Fast Jolt of Throughput
Read to learn more about how PCIe supports the demanding requirements of AI accelerators.
PCIe 6.x Simulation and Electrical Testing for High Data-Bandwidth Applications
Don't miss this Synopsys and Tektronix webinar, hosted by SemiWiki.
World's Most Interoperable PCIe 6.x and Beyond at PCI-SIG DevCon 2023
See successful PCIe 6.0 interoperability demos in our booth & our partners’ booths. Don’t miss our demo at 128 GT/s as we take a peek into the PCIe 7.0 tech and make sure to watch the world’s first PCIe 6.0 RX link training compliance tests.
Synopsys PCIe 6.x End-to-End Link Traffic Analysis at PCI-SIG DevCon 2023
Rehan Iqbal, Sr. R&D Engineer, takes a deep dive of our PCIe 6.0 End-to-End demo. See an in-depth demonstration our link traffic analysis using Teledyne LeCroy's interposer & analyzer.
How to Maximize PCIe 6.x’s Advantages with End-to-End PCIe Design Solutions
Leveraging IBIS-AMI Models to Optimize PCIe 6.x Designs
PODCASTS