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Verification IP for DDR5/4 NVDIMM-P
Synopsys® VC Verification IP for JEDEC DDR5/4 NVDIMM-P provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DDR5/4 NVDIMM-P based designs.
Synopsys VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affect performance and ease-of-use. It can be integrated, configured, and customized with minimal effort, enabling designers to easily expand usage and meet organizations requirements. This VIP is natively integrated with Verdi® Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Highlights
- Native SystemVerilog/UVM/OVM
- Memory model certification
- Access to vendor specifications and memory models
- Runs natively on all major simulators
- All JEDEC parts
- Runtime JEDEC and vendor part selection
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi Protocol and Memory Analyzer
- Dynamic reconfiguration
- Backdoor memory/mode registers access
- Bypass/fast initialization
- Error injection and exceptions
- Trace file and debug ports for easy debug
- Delay modeling: fly by delay, trace delay, buffer delays
- Overriding timing parameters
Features
All commands
- READ/Write command
- Power Entry/Exit
- Flush
- READ STATUS
Random Read Response delay Modeling
Random response delay modeling for FLUSH/PWRITE
Support for Out of Order Read commands
Support Shared AWB/PWC/CTH and WGID bitmap
Poison bit
Supports Metadata options
IOP packet trigger control
Call back hooks for important event notification
- Commands started and Data completion notification
Static/Dynamic reconfiguration for timing and configuration setting
Skew Support (DQ/DQS pins)
Tested against vendor models
Built-in protocol and timing checks
Functional coverage model and verification plan
Analysis port for score-boarding
Verdi Protocol and Memory Analyzer