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VC Verification IP for MIPI I3C
Synopsys® VC Verification IP for MIPI I3C provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of MIPI I3C designs.
Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
Highlights
- Native SystemVerilog/UVM
- Optional source code Test Suites
- Runs natively on all major simulators
- Built-in protocol checks
- Verification plan and coverage
- Verdi® integrated protocol analyzer
- Trace file support for debugging
- Extensive error injection
Key Features
- I3C v1.0 specifications supported
- All topologies
–Single Primary-Single Secondary (I3C/I2C)
–Single Primary-Multi Secondary
–Multi Primary-Single Secondary
–Multi Primary-Multi Secondary - Legacy I2C Secondary agent can be configured as a generic secondary or as an EEPROM secondary
- Dynamic Address allocation
- Common Command Codes
- Transactions as per SDR frame format
- Hot-Join feature
- Interrupt request handling
- High Data Rate—TSP (Ternary symbol pure bus), TSL (Ternary symbol legacy inclusive bus), DDR (Double data rate)