Synopsys UCIe IP Solutions

Synopsys’ complete Universal Chiplet Interconnect Express (UCIe) IP solution, including controller, PHY, and verification IP, offers high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package. The PHY has achieved silicon success on multiple advanced foundry processes and completed successful interoperability with third-party devices. The PHY’s flexible architecture supports standard and advanced packaging technologies, delivering up to 5Tbps bandwidth in a multi-module configuration. The Synopsys parallel die-to-die interface is capable of operating at up to 40GT/s data rates with a low bit error rate. Synopsys UCIe Controller IP supports widely used protocols such as PCI Express and CXL and enables latency-optimized NoC-to-NoC links with streaming protocols. Synopsys UCIe Controller and PHY IP solutions enable robust and reliable die-to-die links with testability features for known good dies and CRC or parity checks for error correction. Synopsys VIP for UCIe enables verification for all topologies and at all signaling interfaces of a UCIe design.

Additional Resources
Video: Synopsys UCIe IP Showing Excellent Die-to-Die Performance at 24GT/s
Blog: Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip
Blog: UCIe Standard: Benefits & Requirements Explained

Synopsys UCIe Controller IP Datasheet
Synopsys UCIe PHY IP Datasheet