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Verification IP for LPDDR5
Synopsys® Verification IP for JEDEC LPDDR5 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of LPDDR5/4/3/2 based designs.
VC VIP LPDDR5 is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affect performance and ease-of-use. The VIP can be integrated, configured, and customized with minimal effort, enabling designers to easily expand usage and meet organizations requirements. VIP is natively integrated with Verdi® Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Highlights
- Native SystemVerilog/UVM
- Memory model certification
- Access to vendor specification and memory models
- Runs natively on major simulators
- Runtime JEDEC and vendor part selection
- Verification Plan and Coverage
- Built-in protocol and timing checks
- Verdi Protocol and Memory Analyzer
- Dynamic reconfiguration
- Backdoor memory and mode registers access
- Trace file and debug ports for easy debug
- Bypass/fast initialization
- Error injection & exceptions
- Delay modeling: Fly by Delay, Trace Delays
- DFI monitor
Features
LPDDR5 Specification JESD209-5A/ JESD209-5B/ JESD209-5C
8/16 bank and bank group modes
All data rates (533 –6400 Mbps)
Memory densities (2GB to 32Gb)
Multi rank checks & coverage
All commands
All mode registers
All LPDDR5/5x trainings
Configurable refresh rates
Write-X, DSM, ECC and data copy
WCK2CK synchronization (4:1/2:1 ratios)
Temperature derating support
All the core timings
LPDDR5X new data rates (7500 Mbps, 8533 Mbps, & 9600 Mbps) latencies (RL/WL/nWR etc.)
LPDDR5X E-DVFSC support
DCA/RDCA/DCM
CA/CK/CS ODT
DFE/ Per-pin DFE
ODT/ NT-ODT
CK/WCK/RDQS Single Ended Mode
ZQ Calibrations
Data Bus Inversion and Masking
Refresh Management (RFM) support
All commands
- MRW/MRR, RD/WR, ACTIVE, MPC
- PDE/PDX, SRE/SRX/DSM
- Other additional commands
All LPDDR5 trainings
- CA Training (mode1 and mode2)
- RD/WR FIFO
- WCK2CK leveling
- Read DQ calibration
- Read-Write based WCK-RDQS_t Training, RDQS Toggle Mode, Enhanced RDQS Toggle Mode, WCK-RDQS_t/Parity Training
ZQ calibration
- Command based
- Background calibration
DVFS(DVFSC, DVFSQ)
Data Bus Inversion and masking
Frequency set points
- Low, medium and high frequencies
All Mode Registers support covering the settings like
- WL/RL, Preamble and Postamble, and RDQS mode
x16 Mode, Byte Mode and Mixed mode Support
Other Features
- DFE, PASR, PARC, PPR, ODT/NT-ODT and related timings support
- Single ended CK/WCK/RDQS, Enhanced WCK-Always ON mode support
- Write X Steering Control bits
- Mixed mode support with configurable upper and lower byte mode devices
- tWCK2DQI and tWCK2DQO oscillators
- Optimized Refresh
- LPDDR5X Adaptive Refresh Management (ARFM)
- LPDDR5X Read Duty Cycle Adjuster (RDCA)
- LPDDR5X CA/CK/CS ODT
- LPDR5X per-pin DFE
- LPDDR5X Directed Refresh Management (DRFM)
- LPDDR5X Enhanced DVFSC (E-DVFSC) mode
Callback hooks for important event notifications
- Cmd and data completion notifications
Access to internal states of the model
Static/dynamic reconfiguration for timing and configuration settings
Skew support (WCK and DQ/DMI/DBI pins)
CLK and WCK jitter
Jitter in driving data window (RD cmd)
Vref DQ eye feature independent for each DQ pin
- Data driving (Read)
- Data sampling (Write)
PVT modeling for twck2dqi and twck2dqo variation
User configurable logical addressing
Customized setup/hold violation checks
Tested against vendor models
Built-in protocol and timing checks
Functional coverage model and verification plan
Analysis port for score-boarding
Synopsys Verdi Protocol Analyzer and Performance Analyzer
JEDEC and Vendor Part Numbers
Synopsys VIP supports generic JEDEC part numbers with densities ranging from 8Gb to 32Gb, data rates up to 8800 Mbps, and bus width from X4 to X16. It supports core timings according to specific frequencies and densities. Synopsys collaborates with leading memory vendors, including Samsung, SK Hynix, Micron, and Nanya for support of specific vendor part numbers, as they are made available. It also provides a configuration to model all possible JEDEC part numbers virtually. The virtual part number feature enhances productivity, as user need not to request and wait for delivery of the required part number from Synopsys.