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VC Verification IP for DDR3
Synopsys® VC Verification IP for the JEDEC DDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on DDR3 based designs. VC VIP DDR3 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP DDR3 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
DDR3 SDRAM and DIMM Protocol Features
- JESD79-3F DDR3, JESD79-3-1A-01 DDR3L and JESD79-3-2 DDR3U JEDEC
- SDRAM device standards
- MRAM support
- Built-in UDIMM, SODIMM, RDIMM, and LRDIMM
- 512Mb to 8Gb densities and x4, x8 and x16 wide SDRAM devices
- BL switch on the fly, 8 banks, 8 bit pre-fetch
- Write leveling, read leveling, jitter, auto self refresh
- Address mirroring
- Delay modeling : Fly by Delay, Trace Delays, Pre and Post buffer delays
- DFI monitor
VIP Highlights
- Native SystemVerilog/UVM
- Runs natively on all major simulators
- Verdi Protocol-aware debug
- Built-in verification plan and coverage
- Built-in protocol and timing checks
- Runtime JEDEC and vendor part selection
- Overriding timing parameters
- Backdoor memory access
- Bypass/fast initialization
- Error injection & exceptions
- Trace files and debug ports
- Configuration creator GUI