Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip

Lessons Learned to Move Multi-Die Systems Forward

Multi-die systems are becoming an answer for many application areas as bandwidth demands soar to new heights. Through heterogeneous integration of multiple dies in a single package, a multi-die system delivers greater levels of processing power and performance for AI, high-performance computing, and hyperscale data centers. An array of technological innovations has paved the way for the emergence of multi-die systems, a critical one being the UCIe standard. Introduced in March 2022, UCIe is considered the de facto standard for die-to-die connectivity, helping to enable a broader ecosystem of vetted dies, or chiplets.

Through their collaboration, the Synopsys and Intel teams uncovered some lessons learned that they plan to share with the UCIe Consortium, which oversees the standard and is developing a compliance program for the standard. Among some of the lessons:

• As silicon design and manufacturing become more complex, and validating that everything works as intended is also cost- and time-intensive, finding a way to use existing test chips or silicon can be an ideal way to assess compatibility.
• Designing multi-die systems involves extensive planning, especially if you plan to re-use package or board designs. Building in as much flexibility as possible in the boards is one way to provide options for future use.
• An open standard like UCIe provides confidence of interoperability. When one company controls both sides of a link, there are, of course, no concerns about whether each side will work together. But moving forward, we’ll likely start seeing more companies who prefer not to build both sides, instead choosing to buy components off the market.
• By allowing partitioning of a design to include multiple process nodes, chiplets help to mitigate the expense of manufacturing at advanced nodes. Without a standard, IP availability is limited, and choosing a process node based on IP availability isn’t an optimal approach. The UCIe test chip interoperability demo provides a solid proof point for mixing and matching IP designs and lays the foundation for an open chiplet ecosystem. 

Interoperability Demo Opens Pathways for Custom Silicon

One of the advantages of a multi-die system architecture is that it can consist of dies from different vendors for different process nodes. This provides flexibility in terms of cost and in optimizing power, performance, and area (PPA). UCIe is a key ingredient to bring the disparate components together, enabling them to communicate with one another while supporting a range of advanced packaging technologies. The UCIe Consortium sees UCIe as an enabler of an open chiplet ecosystem. Such an ecosystem could potentially spark new waves of custom silicon innovation to meet relentless performance demands of an era where AI, connectivity, and cloud computing are becoming ubiquitous.

While a UCIe-compliant multi-die system may work well through development, testing, and manufacturing, you’ll also need to ensure that the system’s die-to-die connectivity will remain reliable from the start and in the field. This is where UCIe IP plays an integral role. UCIe IP typically consists of a controller for low latency between dies based on common protocols, such as PCIe, CXS, and Streaming protocols; a PHY for high-performance and low-power connectivity in a package; and verification IP to accelerate verification closure. Built-in testability features enable you to root out defective dies at the naked die testing phase. In addition to these testability features for known good dies, the IP can also provide cyclic redundancy checks (CRC) or parity checks for error detection and retry functionality for correction of detected errors.