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VC Verification IP for HDMI
Synopsys VC Verification IP for HDMI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of HDMI designs. It supports changing of video and audio related configurations during simulation and also enables easy addition of new video formats.
Protocol Features
- HDMI 2.1 (r102 version), 2.0a, 2.0, 1.4b and 1.3a
- HDCP 1.4, 2.2 and 2.3
- Compressed video for 2D and 3D using VESA DSC 1.2a
- CEC, ARC, eARC, EDID and DDC support
- Latest CEA-861-G spec Video ID codes
- All video formats, color depths and pixel encodings including YCbCr 4:2:0
- All Data island packet types and HF-VSIF
- DVI compatible, support for VESA DMT IDs
- 10K/8K/4K/2K and all 3D video
- YCC video quantization ranges
- Scrambling above and below 340 MHz
- Multi-view and 21:9 aspect ratio
- 3D and multi-stream audio (up to 32 channels)
- SCDC and character error detection
- 10/20/40 bit parallel interface HDMI 1.4/2.0
- Serial and 18 bit parallel interface support for HDMI 2.1
- 3Gbps/6Gbps bit rate on 3 lanes and 6Gbps/8Gbps/10Gbps/12Gbps bit rate on 4 lanes
- Link Training with 3 and 4 Lanes with all Training patterns.
- Fixed Rate Link (FRL) packet construction, Reed Solomon FEC (Forward Error Correction), Scrambling/Descrambling with LFSR
- 16b18b encoding/decoding with running disparity
- FRL Data Flow Metering support (Single slope and clock level checking as per v102 Spec)
- Extended Metadata Packet support
- Support for new VIC’s (108-219) and new Video Formats
- VRRFVA Support for 3D and Compressed Video
- Custom video frames, Link Training Bypass, HDCP Authentication Bypass, Pixel dumping into PPM/TXT format support