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Verification IP for GDDR6
Synopsys® Verification IP for JEDEC GDDR6 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of GDDR6 based designs. The VC VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. VIP is natively integrated with Verdi® Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottle necks.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Highlights
- Native SystemVerilog/UVM
- Access to vendor specifications
- Runs natively on major simulators
- Runtime JEDEC and vendor part selection
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi Protocol and Memory Analyzer
- Built-in performance analysis metrics
- Dynamic reconfiguration
- Backdoor memory/mode registers access
- Bypass/fast initialization
- Trace file and debug ports for easy debug
Features
GDDR specification JESD205C
16 bank and bank group modes
DDR and QDR data rate support
Memory densities (4Gb to 16Gb per channel)
All data rates (16Gbps/pin, 14Gbps/pin, 12Gbps/pin)
All commands
All mode registers
GDDR6 trainings
RDQS and DQ preamble
EDC half and full rate support
CRC half and full rate support
WRITE Data mask function
Data bus inversion (DBI) & Command Address bus inversion (CABI)
x8/x16 mode configuration
Pseudo-channel mode (PC mode) configuration
Support PRBS
All commands MRS, RD/RDA,LDFF,RDTR, ACT, WOM/WOMA, WDM/WDMA, WSM/WSMA, WRTR, PREpb/PREab, REFab, REFpb/REFp2b, PDE/PDX, SRE/SRX/ , Hibernate SRE, Hibernate SRX, CAT
All GDDR6 trainings
- Command address
- WCK2CK
- Read and write
Data Bus Inversion/Command Bus Inversion
All Mode Registers support covering the settings like WL/RL,CRCWL/CRCRL
x8/x16 mode configuration
RDQS and DQ preamble
EDC Full and Half Rate
CRC Full and Half Rate
Write Data Mask Function
IEEE.1149.1 Boundary Scan
Callbacks for error generation and commands tracking
Access to internal states of the model
Static/dynamic reconfiguration for timing and configuration settings
Skew support (WCK and DQ/DBI pins)
User configurable logical addressing
Customized setup/hold violation checks
Built-in protocol and timing checks
Functional coverage model and verification plan
Analysis port for score-boarding
Synopsys Verdi Protocol Analyzer and Performance Analyzer
JEDEC and Vendor Part Numbers
Synopsys VIP supports generic JEDEC part numbers with densities ranging from 8Gb to 32Gb, data rates up to 8800 Mbps, and bus width from X4 to X16. It supports core timings according to specific frequencies and densities. Synopsys collaborates with leading memory vendors, including Samsung, SK Hynix, Micron, and Nanya for support of specific vendor part numbers, as they are made available. It also provides a configuration to model all possible JEDEC part numbers virtually. The virtual part number feature enhances productivity, as user need not to request and wait for delivery of the required part number from Synopsys.