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VC Verification IP for eMMC
Synopsys® VC Verification IP for eMMC provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of eMMC based designs. VIP can be integrated, configured and customized with minimal effort and time. Testbench development is accelerated with the assistance of built-in verification plans, example tests and functional coverage. VIP is natively integrated with Verdi® Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
Highlights
- Native SystemVerilog/UVM/OVM
- Optional source code test suite
- Runs natively on all major simulators
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi protocol-aware debug
- Overriding timing parameters
- Backdoor memory access
- Bypass initialization
- Error injection and exceptions
- Trace files and debug ports
- Configuration creator GUI
Key Features
- JEDEC eMMC v5.1, 5.0, 4.5, 4.41
- Card and Host Model
- All data widths (1,4 and 8)
- All speed modes
- Memory density support
- Single and multiple block transfers
- Normal and alternate boot operation
- Lock/Unlock, Tuning and general purpose commands, Data removal commands, Packed commands
- Interrupt support
- Data Tagging, Context management, Partitioning, all protection mechanisms, Bus testing, Power saving sleep mode
- Command Queue, Enhanced Data Strobe