Electrical Layout Verification 

Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems

Synopsys Acquires Silicon Frontline Technology

Full-Chip CDM Analysis: Is Static Simulation Enough?

Efficient Power Semiconductor Devices – A Critical Success Factor for Today’s Low Power Electronics

Verification Methodologies for Domain Crossing and Transient Latch-up Damage Prevention

Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level

Numerical Simulation of Metal Interconnects of Power Semiconductor Devices

Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level

System Aware ESD Design System Mindset For A Better Foundry

Optimizing Power IC Layouts by Simulation Tools

Low-Cycle Fatigue of Multilayer Metal Stack Employed as Fast Wafer Level Monitor for Backend Integrity

A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures

Influence of Ti-Al(Cu) Backend Layer Scheme on Repetitive-Power-Pulsing Robustness

Analyze Power Nets Early and Often with P2P

Accurate Capacitance and RC Extraction Software Tool for Pixel, Sensor, and Precision Analog Designs

RMAP – Software for Resistance Verification of Power Netsand ESD Protection Structures

Full Chip CDM Simulation w/Package Layout Included for Connectivity & Charge Distribution

Characterization & Monitoring Structures for Robustness Against Cyclic Thermo- mechanical Stress