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VC Verification IP for DisplayPort/eDP
Synopsys VC Verification IP for DisplayPort provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of DisplayPort, VESA DSC, HDCP and eDP based designs.
Protocol Features
- DisplayPort 2.0
- DisplayPort 1.4, 1.3a and 1.2 support
- HDCP 2.2 and 1.x specifications
- eDP 1.4b specifications
- VESA DSC 1.2 and 1.1 specifications
- Serial interface
- 10 bit parallel interface(Bypass PHY)
- Main Link, 1,2,4 lanes
- Aux Channel
- Hot plug Detect (HPD)
- RGB, YCbCr Colorimetric formats
- 18,24,30,36,48 bpp
- Audio 2~8 channels
- Audio/Video info frames
- EDID/DPCD registers
- 3D Stereo Video
- SST data
- Clock recovery
- Scalable architecture to support MST