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Verification IP for DFI
Synopsys® VC Verification IP for DFI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DFI based designs.
Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Highlights
- Native SystemVerilog/UVM
- Active and Passive Component
- Runs natively on major simulators
- Built-in protocol checks
- Built-in verification plan and coverage
- Verdi® protocol aware debug
- Extensive error injection
Features
DFI 5.1 Compliant Passive Monitor VIP, Memory Controller VIP and PHY VIP
- 1:1, 1:2 and 1:4 Frequency Ratios
- Supports Command/Control, Write/ Read Data, Update, Status, Low Power, PHY Master, Geardown/2N, MC to PHY Message, WCK Control Interfaces
- Programmable DFI parameters
DFI Memory Controller VIP
- Built-in reference tests to generate the reset, initialization, command and sidebands traffic on DFI interface
- Flexibility to specify the phase number for driving the command
- Supported for DDR 5/4/3, LPDDR 5x/5/4, HBM 3/2e/2, GDDR6 protocols
- Mode register commands modelling
- Data width(x4/x8/x16/x64/x72) as per the protocol
- Dual channel, Pseudo channel, DIMM
- DBI, CABI, ECC, DM, CRC, Parity, EDC, FSP
- Stack ID, Bank Group Bank/Row/Column Address
- Data Read/Write Command Parity & Parity Latency
- Command to command delay modeling, refresh engine and configurable timing parameters
DFI PHY VIP
- Capabilities to model JEDEC initialization, Power management, In-order commands scheduling, and Modelling of tctrl_delay
- Supported for LPDDR 5x/5, DDR5/4, HBM3 protocols
- Memory clock generation and reset modeling
- Data/DQS driving
Callbacks for error generation and commands tracking
Access to internal states of the model
Static/dynamic reconfiguration for timing and configuration settings
Clock jitter (partial)
2D Vref DQ modeling to mimic real world eye
User configurable logical addressing
Pre buffer and post buffer modeling to enable real world trainings