Our Exciting Custom/AMS Design Program at SNUG World

Day 1 - Tuesday, April 20

Hany Elhak, senior director of Marketing at Synopsys, will kick off the program with an update on the latest circuit simulation for analog, mixed-signal and memory designs.

Next will be a panel discussion in which Aveek Sarkar, vice president of engineering at Synopsys and industry leaders will discuss the future of hardware for circuit simulation - is it more CPUs, bigger memory, the cloud or all the above? Join us and find out!

George Kokai, from NVIDIA, will share an update on the latest design challenges and their impact on simulation.

Kihoon Kim of Samsung Foundry, will highlight a new approach to improve simulation runtime for AMS designs dramatically .

Om Johari, from Intel, will showcase the collaboration workflow between Intel and Synopsys that helps AMS designers to run, analyze and debug circuit simulations in a very interactive and easy-to-use way reducing manual errors.

Kedar Janardan Dhori of STMicroelectronics will highlight the requirements for fault analysis and discuss how ST uses TestMAX CustomFault to ensure functional safety of embedded memory IPs for the automotive market.

Danish Shaikh of Western Digital will provide details how his team achieved more productivity using Custom Compiler, and easily resolved design migration and simulation challenges for their 7nm designs.

Day 1 will conclude with Randy Wolff of Micron Technology sharing a practical user-case on how they utilize comprehensive multi-domain analysis and cutting-edge StatEye with IBIS-AMI models to accomplish the challenging LPDDR5 signal integrity analysis.

Day 2 - Wednesday, April 21

Samad Parekh and Manu Pillai from the Synopsys custom design team will talk about how simulation results analysis is changing in the face of growing analog design complexity. Attend this session and learn about the latest capabilities of our design environment.

Denis Goinard, director of Applications Engineering at Synopsys, will present on how designers can avoid extra design iterations by catching potential electrical issues earlier during design. He will highlight the Synopsys Custom Design Platform’s unified workflow that brings signoff analysis into the design process.

Karun Sharma, director of Applications Engineering at Synopsys will demonstrate how to improve QoR and productivity for your analog layout with Custom Compiler’s productive and easy-to-use features for analog placement, routing and template-based design reuse. We call these technologies visually-assisted layout automation.

Jinman Kang of SK hynix will share how his team reduced design time by 3X after deploying a template-based analog layout flow.

Anjali S from Intel will present how they achieved significant productivity gain by deploying a new schematic-driven layout methodology.

Denis Keane of Xilinx will highlight how Xilinx accelerated their chip integration while improving SPEF quality for timing closure with Custom Compiler. His team is able to increase design reliability and reduce late-phase editing iterations, improving productivity and achieving design closure much faster with in-design analysis.

Seongkyun (Gabriel) Shin of Samsung Foundry will present Samsung’s advanced node AMS design reference flow. The flow demonstrates how Samsung Foundry customers can now take advantage of the most advanced circuit design features, reliability verification, automated layout, block and chip integration to improve design productivity.

Day 2 will conclude with Ofer Tamir of Tower Semiconductor presenting how Synopsys and Tower Semiconductor partner to enable mutual customer success. This collaboration enabled analog, RF and photonics design flows for the customers designing their next generation of products.