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Case Studies accelerating AI applications using custom RISC-V based SIMD/VLIW DSPs
The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the AI acceleration domain, and thus more flexibility and agility in both the design process and the eventual product. By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated.
Synopsys ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP. Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain.
This seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms, such as specialization, SIMD, and VLIW, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM).
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Who Should Attend?
If you are a design engineer, algorithm developer, software engineer, system architect, or design manager focusing on advanced SoCs requiring application-specific optimizations, you won’t want to miss this event.
Agenda
An Introduction to ASIP Designer
7:00 a.m. - 7:30 a.m. PT
Falco Munsche, Technical Product Manager ASIP Tools, Synopsys Germany
Application-specific processors (ASIPs) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs and will provide an overview of Synopsys' ASIP Designer tool-suite.
ASIP Architecture Features for AI Applications
7:30 a.m. - 7:50 a.m. PT
Werner Geurts, Dir. Applications Engineering ASIP Tools, Synopsys Belgium
In this session, we will address architecture features that are commonly used to accelerate AI applications, and which are well supported in ASIP Designer. These features include instruction level parallelism, data level parallelism or SIMD, and custom functional units. We will address the modelling of these features, the use of the compiler and the generation of optimized RTL code.
Case Study: Tact, An ASIP for Accelerating Swish and RMSNorm
7:50 a.m. - 8:10 a.m. PT
Khawar Shahzad, Staff Applications Engineer ASIP Tools, Synopsys Germany
In this session we will present a case study on the design and implementation of an ASIP aimed at accelerating swish and RMSNorm, these two algorithms are well-known and widely used in the AI/NN domain.
Starting from functional and architectural requirements, we shall clarify the reasoning behind design designs and how the ASIP Designer tool helped with creating an efficient processor architecture and optimal C-language applications code containing custom data types.
Case Study: smarT, An Efficient ASIP for Medium-Complexity AI Applications
8:10 a.m. - 8:30 a.m. PT
Erik Brockmeyer, Principal Applications Engineer ASIP Tools, Synopsys Belgium
This session presents an efficient ASIP for Edge-AI application using the Tensor Flow Light for Microcontroller (TFLM) framework. The specialization and extension a simple RISC-V processor improved the performance by 350x, whereas the logic increase is just 7x. The core exploits Instruction Level Parallelism (ILP), specialized instruction/registers, small vectors (SIMD), resource sharing and other techniques to reach this goal. The local memory bandwidth requirements could be reduced significantly by carefully reusing data in the ASIP register files. Similarly, a low overhead DMA and circular Addressing Generation Units (AGU) enabled small and efficient local memory usage. The ASIP tools provide good control over the processor architecture and provide feedback to make the relevant design tradeoffs.
Q&A
8:30 a.m. - 9:00 a.m. PT
Meet The Presenters
Falco Munsche
Technical Marketing Manager
Synopsys
Falco Munsche is the Technical Product Manager for ASIP design tools at Synopsys. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University.
Werner Geurts
Director of Application Engineering
Synopsys
Werner Geurts is Director of Application Engineering for ASIP design tools at Synopsys. In this role he is responsible for the technical support for Synopsys’ ASIP design tools and for evaluations projects. Before joining Synopsys, he co-founded Target Compiler Technologies, a pioneering company providing retargetable tools for the design of application-specific processors. Between 1989 and 1996, Werner Geurts was a researcher at IMEC, where he has been working on behavioral synthesis of data-path structures and on retargetable compilation. Werner has co-authored several papers in electronic design automation. He holds master's degrees in electrical engineering from the Hogeschool Antwerpen and K.U. Leuven, and a Ph.D. degree from K.U. Leuven, since 1985, 1988, and 1995 respectively.
Khawar Shahzad
Staff Applications Engineer
Synopsys
Khawar Shahzad is a Staff Applications Engineer for ASIP design tools at Synopsys. He earned his MSc degree in electrical engineering from RWTH Aachen university and has more than 10 years of experience in the field of microprocessor design and embedded systems.
Erik Brockmeyer
Principal Applications Engineer
Synopsys
Erik Brockmeyer is a Principal Applications Engineer for ASIP design tools at Synospys. He received his Master's degree in Electrical Engineering in 1998 from the University of Eindhoven, the Netherlands. He worked for 10 years at the Interuniversity Micro Electronics Center (IMEC) on application optimizations for data transfers and storage. Initially his work focused on mapping applications efficient to a memory hierarchy, and later shifted to multi-processor systems with a shared distributed memory. In 2008 he joined Target Compiler Technology as application engineer. In this role he developed many different ASIPs for various application domains. He continued this role when Target was acquired by Synopsys.