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ARC HS Processor Family
Meeting Increasing Processor Performance Requirements in High-End Embedded Applications
Hear Paul Stravers, Principal R&D Engineer, describe how the ARC HS6x superscalar architecture can deliver performance, scalability and flexibility to address increasing performance requirements for a variety of high-end embedded applications.
Maximum Performance for Embedded Applications
The latest additions to the ARC® HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARCv3 instruction set architecture (ISA). The previous generation HS processors, based on the efficient ARCv2 instruction set architecture (ISA), include the HS3x, HS4x, and DSP-enhanced HS4xD processors. All HS processors support closely coupled memories (CCMs), which enable single-cycles access to instructions and data.
HS processors are optimized for GHz+ operating speeds with minimum area and power consumption, making them ideally suited for embedded applications with very high-performance requirements. The HS processors are available in single-core, dual-core and quad-core configurations.
The ARC HS processors are supported by a broad ecosystem of commercial and open-source tools, operating systems, and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website.
ARC HS34/HS36/HS38
For use in embedded applications requiring high performance efficiency
• Optimized 10-stage pipeline
• L1 coherency, L2 up to 8 MB
• Efficient software development
ARC HS44/HS46/HS48
Superscalar architecture for high-performance embedded applications
• High-speed, dual-issue pipeline
• Full MMU, 40-bit address
• Single-, dual-, quad-core versions
ARC HS45D/HS47D
Dual-issue, 32-bit, RISC + DSP architecture for high-performance embedded applications that require signal processing
• Combined RISC + DSP processors
• Over 150 DSP instructions
• Easy DSP programming support
ARC HS46FS/HS47DFS/HS48FS
Dual-issue processors for high performance automotive applications
• Error detection and correction code
• Single-, dual, and quad-core implementations
ARC HS56/HS57D/HS58
32-bit superscalar architecture for high-end embedded applications
• 32-bit ALU and core registers
• 32-bit virtual, 40-bit physical address space
• Scalable up to 12-core coherent cluster
ARC HS66/HS68
Superscalar 64-bit architecture supports 52-bit physical and 64-bit virtual addresses
• 64-bit pipeline and register set
• Advanced FPU with 128-bit SIMD
• Scalable up to 12-core coherent cluster
ARC Software Development Platforms:
- ARC HS Development Kits
- ARC AXS103 Software Development Platform (complete, standalone platform for software development, debugging, and profiling)
ARC Development Tools and Software:
- MetaWare Development Toolkit (compilers, debugger, and simulator)
- GNU Tools (compiler, debugger, utilities) & ARC Linux OS
- MQX RTOS
- embARC Open Software Platform (comprehensive suite of free and open source software)
- ARC Access Program (portfolio of 3rd party tools, operating systems, and middleware)
ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.
- Harvard architecture for higher performance through simultaneous instruction and data memory access
- High-speed pipeline designed for maximum power efficiency
- 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density
ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.
- Add or omit hardware features to optimize the core for your target application - no wasted gates
- The ARChitect wizard enables drag-and-drop configuration of the core
ARC Processors EXtension (APEX) technology enables users to customize their processor implementation.
- Add user-defined instructions to accelerate software execution and reduce code size, reducing energy consumption and memory requirements
- Tightly couple memories and peripherals to the processors to eliminate the need for additional bus infrastructure, reducing area and latency and increasing system-level performance