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How to Radically Improve Analog Layout Efficiency with Highly Reusable User-Defined Devices
Author: Soni Kapoor, Sr. Technical Marketing Manager, Custom Design and Physical Verification Group
I’m always excited to hear stories from customers that are deploying advanced techniques with Custom Compiler™ to improve their productivity. As you know, analog design is getting tougher and with tight design schedules, designers need to be really creative to meet their project deadlines.
One clever presentation I heard recently was from Endura Technologies at this year’s SNUG. They gave a presentation called “Radically Improving Layout Efficiency through the Use of User-Defined Devices (UDD)”. They highlighted how they love the intuitive nature of Custom Compiler’s visually-assisted layout automation and used its powerful capabilities for their embedded power management IC (PMIC) designs. The team developed highly reusable and programmable complex layout blocks on various technology nodes and said they achieved a 2X reduction in effort compared to their previous technique.
I strongly recommend watching the video of their presentation by Jack Quinn, senior IC layout designer. It is now available on-demand at https://www.synopsys.com/community/snug/snug-world/location-proceedings-2021.html
The key Custom Compiler feature they used to achieve the improved productivity is called UDD. Let me tell you more about it.
What is UDD and why it is needed?
Parameterized Cells (PCells) are used as flexible building blocks for analog and mixed-signal layout for increasing productivity. Typical PCell usage is for process design kit (PDK) primitive devices.
But PDKs don’t provide the specific variants (e.g., layout only cells – TAPs, DeCaps, fillers and guard rings). Also, layout designers often create custom structures around PDK PCell (e.g., creating customized routes for easy connections or extendable power/ground (PG) mesh that can be used per instance). All of these customized layout structures take time to build and often not reusable without extra effort.
Historically, programming language expertise has been required to create complex PCells that function reliably and efficiently. Simple GUI-based tools for PCell creation have been available, but the usage was constrained to very simple structures and the solution was not scalable with increased complexity.
The principle behind PCells can be extended to generate common analog building blocks for the same benefits of efficiency, uniformity, and ease of maintenance.
Custom Compiler UDD is a graphical environment for PCell generation by layout designers within their familiar layout environment. There is no need for programming, and the users intuitively create the complex programmable layout structures just like they have been creating custom layout.
Learn more about this cool technology in one of our technical video series by Synopsys Scientist, Shabbir Batterywala here: https://www.synopsys.com/implementation-and-signoff/custom-design-platform/video-whitepapers.html
To summarize, PCells for layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct by construction layout and are the most important ‘power’ tool for custom/analog layout designers.
With increasingly tougher analog design deliveries, now it was a perfect time to take that PCells’ power to another level by unleashing fresh wave of innovation, new methodologies and workflows, with Custom Compiler User-Defined Device (UDD).
I hope you enjoyed this information. Talk to you in another post!